OpenPiton Release 7

Posted on by Jonathan Balkind

OpenPiton release 7 (18-06-21-r7) is now available. Headline features of release 7 are:

  • Inferring all BRAMs: Now you can easily change the size of the caches for FPGA implementations. This also makes porting OpenPiton to new FPGA boards much simpler.
  • Chipset/IO crossbar: Define the devices you use in an XML file and all P-Mesh NoC connections will be generated automatically.
  • Zeroing memory in hardware: This reduces boot time – booting to a bash shell now takes only two minutes (full system boots in <10 minutes).
  • Printing from C/assembly: Your print statements in C/assembly will now be output to a simulated UART.
  • Development VM: A pre-packaged environment to quickly get started with OpenPiton using the open-source Icarus Verilog simulator. (Coming in a couple of days!)

Download Page

We presented our power characterization of the Princeton Piton processor at HPCA ’18 and made the PCB design as well as the power and energy characterization data openly available.
Please post in our Google Group if you have any questions or issues with the platform. We are full of ideas for release 8 and want your input. Get in touch if there’s something you’d like to add.