We have great news for fans of open source hardware: The Princeton Parallel Group led by David Wentzlaff, and the Digital Circuits and Systems Group of ETH Zürich led by Luca Benini have joined forces to bring you the OpenPiton open-source research processor platform with first-class support for 64-bit Ariane RISC-V cores. The latest update of the open-source Ariane processor, (Ariane IV) now supports the P-Mesh cache system from OpenPiton, and with today’s OpenPiton release 10 (18-11-29-r10), we have our first working system. Going forward, OpenPiton will be the go-to multicore environment for Ariane. Likewise, Ariane will have first-class upstream support in OpenPiton. Together, OpenPiton+Ariane provides the ideal permissive open-source RISC-V system that scales from single-core to manycore.
Make sure to check out OpenPiton on GitHub to see how to simulate OpenPiton+Ariane and run C programs in manycore configurations. All available to download under permissive open source licenses. We are not done yet: an FPGA implementation for Genesys2 and an SMP Linux-capable configuration are not far away – stay tuned!
Follow us on twitter (@openpiton) and (@pulp_platform) for up-to-date news.
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