What is JuxtaPiton?
JuxtaPiton is (to our knowledge) the world’s first open-source, general-purpose, heterogeneous-ISA processor. It is an enhancement to OpenPiton, built by integrating the PicoRV32 RISC-V core, written by Clifford Wolf, into the OpenPiton framework. JuxtaPiton inherits all of the capabilities of OpenPiton, with the added ability to instantiate chosen tiles with RISC-V cores, rather than the usual OpenSPARC T1 core, which uses the SPARC v9 ISA. The PicoRV32 core is connected to OpenPiton’s L1.5 cache, making it cache coherent with other cores in the system, thanks to our P-Mesh cache coherence protocol.
When implemented on FPGA, JuxtaPiton can boot Debian Linux on an OpenSPARC core as with OpenPiton. With the addition of a PicoRV32 core in the system, the OpenSPARC core can offload the execution of RISC-V binaries to be natively executed on the PicoRV32 core. When the RISC-V binary needs to make a system call, it can proxy it on the OpenSPARC core instead. This is done through shared memory as provided by P-Mesh.
To validate the integration of the PicoRV32 core in simulation, we have added the option to run the RISC-V assembly tests provided with PicoRV32 inside the OpenPiton infrastructure. You can use the existing commands and tools to run these tests, and add any new tests you might want to validate the functionality of your OpenPiton modifications.
JuxtaPiton will be presented in a poster at FPGA 2019. The paper which accompanies this poster is now available on arXiv. The primary author of this work, Katie Lim, also presented JuxtaPiton at the Student Research Competition at MICRO 2018, where she won first prize for the undergraduate research category.
We hope that JuxtaPiton will provide a useful platform for heterogeneous-ISA processor research and we welcome further contributions from the community. If you find this work useful, please cite our FPGA/arXiv paper and let us know. Our thanks go to Clifford Wolf for creating the PicoRV32 core and making it available open source.
How to use JuxtaPiton
JuxtaPiton is available as part of OpenPiton release 9 (18-11-20-r9). You can download it from the OpenPiton website or clone it on GitHub.
Simulation
If you want to run assembly tests on the PicoRV32 tile alone, you can use the -pico argument to the sims build. At the moment, only the tests distributed with PicoRV32 are supported, rather than the whole of the riscv-tests repository. After adding a RISC-V RV32I cross-compiler to your path, you can run all of the supplied tests with the command sims -group=pico_tile1 -sim_type=vcs (replacing vcs with icv/ncv/msm if you would prefer to use Icarus Verilog, Cadence Incisive, or Mentor Modelsim to run the simulations). To check the status of the tests, cd to the dated folder created by running the provided command, then run regreport $PWD >report.log which will output the status of each of the tests to the file report.log. You can then read the file’s contents to see which tests pass, fail, or timeout.
To try out PicoRV32 tiles alongside OpenSPARC tiles in simulation, pass the flag -pico_het to the sims build. We do not presently provide a software infrastructure for testing the FPGA-equivalent functionality in simulation at present. Instead, you will need to manually tinker with the simulation if you want to make the OpenSPARC tile wake up the PicoRV32 tile and have it run tests like the loader program enables you to do on FPGA.
Instantiating Cores for FPGA
The number of tiles and whether or not PicoRV32 tiles are instantiated in a design are controlled by options in piton/design/xilinx/pyhp_setup.tcl. The actual selection of which tiles are SPARC tiles vs RISC-V tiles is controlled in piton/design/chip/rtl/chip.v.pyv where the tiles are instantiated. A TILE_TYPE parameter is passed into each tile instantiation and propagated from there to appropriate parts of the hierarchy.
The tile instantiation is such that tiles with an odd ID are PicoRV32 tiles and tiles with an even ID are SPARC tiles. The provided FPGA bitfile was built with 2 tiles with PicoRV32 tiles turned on, so tile 0 is a SPARC tile, and tile 1 is a PicoRV32 tile.
FPGA Build
The use of PicoRV32 tiles can be toggled with the define PITON_PICO_HET in piton/design/xilinx/design.tcl
To build the same design as the provided bitfile, you should first add PITON_PICO_HET and NO_RTL_CSM to the list of defines in piton/design/xilinx/design.tcl
Next, in piton/design/xilinx/pyhp_setup.tcl you should set PTON_X_TILES to 2, PTON_NUM_TILES to 2, and uncomment the PICO lines in the file which enable the PicoRV32 cores.
You can then run the normal command to build a bitstream for FPGA:
protosyn -b genesys2 -d system.
Any other configuration modifications such as number of tiles, size of caches, etc., can be made as normal (see the OpenPiton FPGA manual for more details).
Software Infrastructure
For testing on Genesys2 FPGA, we implemented a user program that runs on the OpenSPARC core to host the PIcoRV32 core. The user program acts as an ELF loader for RISC-V binaries and can also proxy syscalls from the PicoRV32 core when the binaries are linked against a modified version of Newlib. We also added two new syscalls and a new hypercall to the OpenPiton Linux kernel and hypervisor, respectively.
The hypervisor configuration was also adjusted, so that Linux does not use the top 16 MB of memory. This memory is used for initial communication between the SPARC core and the PicoRV32 core.
If you program your Genesys2 FPGA with the provided bitfile and then write a microSD card with the provided OS image, then you will be able to observe the boot process by connecting to the UART on the FPGA board. This process is the same as for OpenPiton and is described in more detail in the FPGA manual.
To use the loader, execute it on the OpenSPARC core and give it a RISC-V binary as a command line argument. You can try it with the pico_ldr and simple_pico_test binaries provided in the juxtapiton-loader repository and on the provided disk image. Boot Linux on the SPARC core, cd to the appropriate directory, then run ./pico_ldr simple_pico_test
This will print a number of lines to the terminal describing what the JuxtaPiton system is doing. Towards the end, the PicoRV32 core will print out “Hello world” by writing directly to the UART. Because it writes directly to the UART, its output will be mixed in with print statements from the OpenSPARC core.
You can also build your own RISC-V binaries to run on the JuxtaPiton system.
Building RISC-V Binaries
To build RISC-V binaries, you’ll have to compile your own RISC-V toolchain. Good instructions are given by Clifford Wolf on the PicoRV32 GitHub page.
Binaries that run on the PicoRV32 core must be statically compiled, because it does not have a dynamic loader. We did this by compiling each C/assembly file separately to object files with the flags -fPIC and -static. We then linked the object files together using the linker script riscv.ld as provided in the juxtapiton-loader repository, and the flag -static.
The linker script is a modified version of the one provided in the PicoRV32 core repository. Because PicoRV32 doesn’t support virtual memory, the start address is modified to be 0x1000. The script also includes commands to pick the appropriate versions of libraries to link with. Currently it links with Newlib, libgloss, and GCC libraries. The modified libgloss library that allows syscalls to be proxied is included in the juxtapiton-loader repo as well.
NOTE: the paths given in the linker script to libraries should be modified to ones that match the location of your libraries
The PicoRV32 core has been modified to put itself back into reset when there is a store to 0xffff_ffff. If you want to run a binary on the PicoRV32 core without resetting the whole FPGA, make sure the last operation in the RISC-V binary is a store to 0xffff_ffff.
You must be logged in to post a comment.